This invention relates generally to the protection of semiconductor devices from electrostatic discharge by the use of pad structures with parasitic metal oxide semiconductor (MOS) transistors.
Electrostatic discharge (ESD) can be a source of destruction for semiconductor devices. Various schemes have been utilized to offer protection against ESD. For example, see Ajiki Tsuneo, "Reliability of IC Device", Nikkagiren Publishing, k.k., July 1988 (third printing, May 1991), page 282, and see Toshiba IC Reliability Handbook, November 1987, page 130 available from Toshiba, k.k. Toshiba Bldg., Shibaura 1-1-1, Minato-ku, Tokyo 105.